Many products need various amounts of memory. Two of the most useful types of memory are high speed, low cost memory typically implemented as dynamic random access memory (DRAM) and non-volatile memory typically implemented as electrically erasable and programmable read only memory (EEPROM) or Flash memory.
This invention relates to non-volatile memory cells being used in conjunction with DRAM memory cells. Micron Technology, Inc. taught in U.S. Pat. No. 5,324,681 which issued to Lowrey et al. on Jun. 28, 1994, that one time programmable (OTP) memory cells could be used to replace laser/fuse programmable memory cells for applications such as OTP repair of DRAMs using redundant rows and columns of DRAM memory cells and OTP selection of options on a DRAM (such as fast page mode (FPM) or extended data out (EDO)). One of the key advantages of that capability is the ability to program the OTP memory cells after the DRAM memory chip is packaged (a decided advantage over previous solutions).
The antifuse integrally combines the functions of a switching element which makes the interconnection and a programming element which stores the state of the switching element, either "off" or "on." Thus an antifuse occupies little space on the integrated circuit, but has the disadvantage of not being reprogrammable. This single-time programmability makes the antifuse difficult to test and unsuitable for a large class of applications where reprogrammability is required.
Alternative programmable interconnects use a metal oxide semiconductor field programmable transistor (MOSFET) as the switching element. The MOSFET is controlled by the stored memory bit of a programming element. Most commonly, this programming element is a dynamic random access memory (DRAM) cell. Such DRAM based FPGAs are reprogrammable, but the programming of the switching elements is lost whenever power is turned off. A separate, non-volatile memory cell must be used to store the programmed pattern on power down, and the FPGA must be reprogrammed each time the device is powered back up.
It is further desirable to implement non-volatile memory cells along with DRAM cells to provided shadow RAM cells. An example of conventional shadow RAM cells is taught in U.S. Pat. No. 5,196,722 issued to Bergendahl et al. on Mar. 23, 1993. However, the process steps involved there are lengthy and do not fit well with an optimized DRAM technology process flow.
The ability to combine DRAM and non-volatile, e.g. EEPROM, styles of memory, especially if little or no additional manufacturing complexity is required, would facilitate a number of cost effective applications, as described above, which do not currently exist or that, heretofore were too costly to be commercially viable.
Thus, there is a need for additional applications for DRAM technology compatible non-volatile memory cells. It is desirable that such DRAM technology non-volatile memory cells be fabricated on a DRAM chip with little or no modification of the DRAM optimized process flow. It is further desirable that such DRAM technology non-volatile memory cells operate with lower programming voltages than that used by conventional non-volatile memory cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation.